1. Field of the Invention
This invention relates to semiconductor memories. More particularly, this invention relates to a boosting technique in the programming of NAND-type non-volatile semiconductor memories.
2. Discussion of the Related Art
Non-volatile semiconductor memories such as EPROMs, EEPROMs, and Flash memories are well known. In such memories, a threshold voltage Vt of a memory cell refers to the minimum programming voltage level that is required to write into the memory cell. When writing (programming) to a selected memory cell in a conventional non-volatile memory array, programming voltages are applied via a word-line (WL) connected to a control gate of the selected memory cell, via a bit-line (BL) connected to a drain of the selected memory cell, and via a select source line (SELS) coupled to a source of the selected memory cell. The combination of programming voltages changes the threshold voltage of the selected memory cell, typically by causing Fowler-Nordheim (F-N) tunneling or channel hot electron (CHE) injection which charges (or discharges) a floating gate in the selected memory cell.
FIG. 1 shows schematically a typical memory array 10 having external bit-lines BLM and word-lines WLN. Memory 10 is made up of multiple xe2x80x9cstringsxe2x80x9d, each of which is a number of serially-connected floating gate transistors. For example, in FIG. 1, a string is shown including memory cells MC1 through MC16 coupled between select drain transistor SD and select source transistor SS. The channels of memory cells MC1 through MC16 form an internal bit-line IBL. Select drain transistor SD selects the string to program and select source transistor SS isolates the string to be programmed from other external bit-lines BLM. The control gates of select source transistor SS and select drain transistor SD are coupled to select source line SELSN and select drain line SELDN, respectively. Select drain line SELDN is coupled to an external supply voltage source, and select source line SELSN is typically coupled to an array voltage source ARRVSS which is typically ground but can be an analog voltage depending on the operating mode. Each control gate of memory cells MC1 through MC16 is coupled to a respective word-line WLN1 to WLN16 which are in turn coupled to a decoder (not shown). (Although sixteen memory cells are shown for string 12, string 12 may contain other numbers of memory cells, for example, 4, 8 or 32 memory cells.)
Each memory cell MC1 through MC16 has a floating gate that is programmed and erased using, for example, Fowler-Nordheim tunneling. In Fowler-Nordheim tunneling programming, electrons are induced into the floating gate of a memory cell (e.g., memory cell MCB) by biasing the control gate of the memory cell to a relatively high voltage and grounding the body region of memory cell. For example, 20 volts is applied at word-line WLN2 and the drain and the source of memory cell MCB are grounded to 0 volts. In Fowler-Nordheim tunneling erasing, the substrate of the selected memory cell, e.g., memory cell MCB, is biased at, e.g., 20 volts, while the control gate of memory cell MCB is grounded driving the electrons from the floating gate back into the substrate.
During programming of memory cell MCB, memory cell MCB is isolated from surrounding memory cells on the adjacent bit-lines and word-lines (e.g., memory cells MC2 and MCD on the adjacent bit-lines BL0 and BL2, respectively, and memory cells MCA and MCC on the adjacent word-lines WLN1 and WLN3, respectively). Typically, surrounding memory cells on the adjacent word-lines are inhibited by applying at their control gates an unselected word-line high state voltage VPASS (e.g., 10 volts), which provides a voltage difference between the control gate and the drain that is insufficient for a write operation. Regarding the surrounding memory cells on the adjacent bit-lines, the selected bit-line BL1 is grounded and the unselected bit-lines BL0 and BL2 through BLM are biased at supply voltage Vcc. Select drain transistor SD for the selected block is similarly biased at supply voltage Vcc and al select source transistor SS is grounded.
A timing diagram for a conventional boosting technique is shown in FIG. 2. Internal bit-lines IBL are pre-charged to the supply voltage Vcc (e.g., 3 volts) minus the threshold voltage Vt (e.g., 1 volt). The unselected word-lines WLN1 and WLN3 through WLN16 are pumped from source voltage Vcc to their high voltage VPASS (e.g., 8 to 10 volts). Concurrently, the selected word-line WLN2 is pumped from voltage source Vcc to programming voltage VPROG (e.g., 16 to 19 volts). During ramping, the internal bit-line IBL1 through IBL15 are boosted to a voltage proportional to the coupling ratio times the voltage change in the word-line voltage. Since fifteen of the sixteen word-lines, i.e. word-lines WLN1 and WLN3 through WLN16, go to their high voltage VPASS and only one word-line, i.e. WLN2, goes to the programming voltage VPROG, the internal bit-line IBL1 through IBL15 boosting potential is primarily a function of high voltage VPASS. Experiments have shown that the extra boosting by the selected word-line WLN2 pumping to programming voltage VPROG is shared by all 16 memory cells MC1 through MC16. Hence, the contribution to the boosting potential from the extra boosting is small. Since boosting is only needed in a narrow region around a memory cell to be programmed in order to isolate that memory cell, dividing the extra boosting potential among all memory cells is inefficient.
Another concern for a volatile memory is xe2x80x9cprogram disturbxe2x80x9d in an unselected memory cell, due to the high bit-line voltage and the word-line voltage in the selected memory cell. In program disturb, the threshold voltage of an unselected memory cell is changed by Fowler-Nordheim tunneling induced by the large voltage difference between the floating gate and the drain or the control gate of the unselected memory cell. Program disturb can accumulate through repeated programming of memory cells in the same word-line or bit-line, and in some instances may actually change the stored value in the unselected memory cell.
In NAND programming, program disturb can occur between a selected bit-line and an unselected word-line, or between a selected word-line and an unselected bit-line. The maximum boosting potential is limited by the coupling ratio and the maximum unselected word-line high state voltage VPASS that can be applied without disturbing the selected bit-line.
A method is provided for boosting the potential in the channel of a memory cell on a selected word-line without creating program disturb. Under this method, a first voltage is applied to the word-lines of all memory cells. Then, while maintaining the first voltage on a selected word-line, applying a second voltage to the word-lines adjacent the selected word line. Then, while maintaining the second voltage on adjacent word-lines, applying a third voltage to the selected word-line. In one embodiment, the second voltage is a ground voltage, the third voltage is a programming voltage, and the first voltage is a voltage intermediate between the programming voltage and the ground voltage. In one embodiment, a time delay is provided between the adjacent word-lines attaining the second voltage and the application of the third voltage on the selected word-line.
In one embodiment, the memory cells include floating gate transistors.
The present invention allows a selected memory cell to be isolated before application of the programming voltage. The isolation allows a more efficient boost in potential in the internal bit lines adjacent the selected memory cell.
The present invention may be better understood upon consideration of the detailed description below and the accompanying drawings.